The present invention relates to semiconductor logic LSI devices and, more particularly, to a system for designing a cell-layout of a polycell LSI having arrays of high-speed logic components for performing arithmetic and logical operations on data to be processed by a computer.
Recently, great efforts have been made to develop logic LSIs which offer the best possible performance vis-a-vis executing desired arithmetic logic functions. An important aspect of the logic LSI designer's job is the constant search for the best possible trade-off between cost and performance.
To provide a logic LSI capable of performing of the desired logic function, two basically different approaches exist. The first approach is to make a custom-made LSI, in which an optimum logic circuit having an exclusive hierarchical layout of logic elements, which conforms to a desired design specification, is fabricated on a chip substrate, by a known micro-patterning technique. Such a custom-made LSI can be effectively designed, to meet all the user's requirements of a desired logic function. This custom-made LSI, however, suffers from drawbacks, in that its design time is long, the manufacturing cost is high, and functional flexibility is extremely limited, thereby involving high risk on the part of a user.
The second approach is to produce a "gate-array LSI" (also known as a "master-slice LSI"), a "standard cell LSI" (also known as a "polycell LSI"), or the like. Such a semi-customized LSI can be manufactured in a short time and at a low cost, since a common chip substrate having cell arrays can be used to provide various types of logic LSIs of different functions. The function of each chip can be altered merely by adding a different wiring pattern to the chip. Hence, the semicustom LSI has considerable functional flexibility.
In particular, polycell LSIs have a wide functional flexibility and also a high integration density. Year by years, they are attracting more and more of the attention of semiconductor manufacturers. Unlike a gate-array LSI, a polycell LSI requires no mask patterns to form standard cell arrays. Further, the size of its wiring region, known as a "channel," located between the cell arrays on the chip, is not limited. This offers increased flexibility regarding the wiring pattern design.
In the polycell LSI, polycells, such as inverters, 3-input NOR gates, and flip-flops, are arrayed on the chip substrate. To customize the chip, a wiring pattern is used which has been designed so as to form an arithmetic logic circuit performing the specific function desired by the user.
In the conventional method of designing the wiring pattern for a polycell LSI, it is very important for the designers to arrange polycells on a chip substrate, such that (i) the chip substrate can be as small as possible and (ii) the selected standard cells can be effectively connected by way of the shortest possible lines. However, designers often find it necessary to use some wiring lines which extend across any cell array which is located between other two arrays, to electrically connect the selected polycells included in these two arrays. In this case, these lines (known as "through-lines") are limited in number with respect to each cell array. If more through-lines than are allowed are used, polycells having equivalent electrical terminals but unable to perform logic functions, (known as "through-cells") must be added to the cell array. The addition of through-cells, through which the excess lines can extend, increases the length of the cell array. In consequence, the integration density of the LSI must decrease, and a larger chip substrate must then be used.
These problems associated with the known method of designing the wiring pattern for a polycell LSI are a bar to the effective designing of high-performance polycell LSIs for performing desired logic functions.